Over the last few decades, developments in semiconductor fabrication techniques have enabled the fabrication of increasingly smaller electronic components. The increased packing densities of electronic elements achievable in a circuit plane result in improved performances of integrated circuits. To meet the ever-increasing demands for higher device performances, however, it maybe necessary to add another dimension to the circuit structures.
For instance, nanoscale switching elements with resistive switching behavior have recently being discovered and are now the focus of intense research and development efforts. The nanoscale resistive switching devices can be used as non-volatile memory cells and can be fabricated in a two-dimensional crossbar structure with a very high cell density to provide a large memory capacity. Even higher memory capacities can be potentially obtained, however, by adding another dimension, i.e., by forming the nanoscale switching devices in multiple planes vertically stacked together. The ultra-high packing density of such a 3D memory structure is expected to be a viable solution for the demands for high information storage and throughput capabilities of future generations of computer applications.
Going from a two-dimensional circuit plane to a three-dimensional structure, however, is not a trivial task. One significant challenge is to find a way to connect the memory cells in the multiple planes such that each memory cell in the 3D structure can be uniquely addressed. A connection scheme that yields a limited addressing space will restrict the number of planes that can be included in the 3D structure. Also, the connection and addressing scheme should not be so complicated to render it infeasible to fabricate the 3D structure or result in poor performances of the memory devices.